This project developed a practicable methodology for predicting reliability of integrated circuit semiconductors used in high reliability applications.
- Developed a simple-to-use, spreadsheet-based reliability prediction tool, using the Physics of Failure (PoF) models from the previous AVSI project, Methods to Account for Accelerated Semiconductor Device Wear Out (AFE 71s1).
- Engaged industry through the Reliability Simulation Council (RSC), an organization founded by semiconductor device manufacturers for development of reliability simulation tools.
Researchers utilized the semiconductor wear out models developed in previous AVSI research to develop an integrated failure rate model. The model was based on the integration of random failure rate models and physics-of-failure (PoF) semiconductor wear out models.
The model provided a capability identified as high priority by members of the aerospace industry in the reliability roadmap that was developed during the Integrated Reliability Processes project. Results integrated with the overall reliability framework developed by that project.
This project has synergy with COTS Assurance Methodsthat investigated utilization and certification of COTS equipment for airborne applications. That project identified outdated reliability assessment methods and life-limited semiconductors as significant problems for the use of COTS electronics.
Researchers coordinated with the RSC to establish a sustainable mechanism for aerospace industry users of complex semiconductor devices to interact with semiconductor device manufacturers, design automation providers, and other semiconductor device users, in a way that will enable accurate aerospace reliability predictions.
Researchers defined a set of common inputs for reliability modeling.
- High Temperature Operating Life (HTOL), or other testing results (# parts, # fails) for a specific part or process and conditions of stress (dynamic stress voltage, temperature, frequency, time),
- Complexity of a subject part relative to those inputs
- Supplier input or industry consensus on a model for scaling random failure rates to other conditions given an identified dominant failure mechanism (e.g. dielectric breakdown),
- The following supplier input on wear out life for subject part or part family:
- Lifetime supported (e.g. 10 years),
- Conditions supported for that lifetime (voltage, temperature, frequency),
- Upper bound to failure fraction at end of life (e.g. 0.1% cumulative distribution function (CDF)) for each important failure mechanism (e.g. time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI), and electro migration (EM)),
- Supplier input or industry consensus on model for scaling wear out failure rates to other conditions and times for each important failure mechanism (e.g. TDDB, HCI, NBTI, EM), which could vary with process generation.
Researchers used the first three items to develop a random failure rate estimate and the last two to develop a conservative estimate of time to a certain failure fraction for each mechanism.
Wear out and random failure rate metrics differ significantly but are often confused and combined together in reliability studies. Causes of wear out failure could be packaging-related, such as material fatigue mechanisms due to mechanical vibration, thermal cycling, and corrosion. Wear out of the silicon device may stem from changes due to electrical stress, radiation, natural degradation, or changes of material properties.
Random failures, in contrast, are caused by intrinsic product defects and singularities in usage stresses, unexpected events or accidents. Mathematically, wear out failure rates tend to increase with time and are characterized by Weibull distributions with slope > 1 while random failure rates tend to be constant with time, characterized by the exponential distribution (the exponential distribution is a special case of the Weibull distribution, in which the Weibull slope is one), or decreasing in time, characterized by a Weibull with slope < 1. Mitigating measures may also differ. Wear out can be moderated by limiting exposure to fatigue environments, but this may not help prevent random failures.
Researchers considered both random and wear out failures, but avoided combining them since these differences limit the usefulness of a single, combined metric. The result of this approach was a reliability model that depended indirectly on internal circuit details.
Analysis below the part level is left to the device manufacturers who own the detailed intellectual property.
Since the project focused on relatively simple time-to-failure scaling models, the result was implemented in a spreadsheet-based tool. Models for additional failure mechanisms (e.g. thermal cycle fatigue of interconnect) can readily be added.
RSC provided three tiers of industry involvement, from the foundry level, device manufacturer level to the OEM/integrator company level. This gave two tiers of interactions and service:
Between foundry and device manufacturers.
Between device manufacturers and OEM/integrators.
The foundry-level involvement enabled detailed technical data from the wafer manufacturing processes to be applied to device manufacturing process and reliability models.
The device manufacturers provided functional-level information to apply the physical mechanisms to establish a rate of functional failure occurrence that provided a device-level failure rate to semiconductor wear out physics of failure models.
The OEM/integrator level involvement linked the information at a high level into a usable database of look-up tables to be used in assembly design and reliability analysis.
There is a definite need for both technology knowledge and application understanding so the appropriate semiconductor failure mechanisms can be represented in reliability models and testing. The AVSI approach to accomplish this was to partner with the semiconductor industry through the RSC to develop communication between the tiers of industry.